1. Field of the Invention
The present invention relates to a semiconductor device having MIS transistors and a method for manufacturing the semiconductor device.
2. Description of the Related Art
“Silicon large-scale integrated circuit” is one of the fundamental device technologies that will support the advanced information society in the future. To achieve high performances from integrated circuits, it is necessary to produce highly sophisticated semiconductor elements such as MISFETs (Metal-Insulator-Semiconductor Field Effect Transistors) and CMISFETs (Complementary MISFETs) that serve as the components of the integrated circuits. Conventionally, the sophistication of devices has been achieved by the scaling rule. In recent years, however, it is difficult to achieve high performances by making devices smaller, due to various physical limitations.
For example, with gate electrodes formed with silicon, there have been problems that the gate parasitic resistance becomes higher as the device operation speed increases, the effective insulating film capacity becomes smaller due to carrier depletion caused at the interface with each insulating film, and the threshold voltage varies due to penetration of impurities into the channel region. To solve such problems, the use of metal gate materials has been suggested.
One of the metal gate electrode forming techniques is the full-silicidation gate electrode technique by which an entire gate electrode is silicided with Ni or Co. Metal gate electrodes need to have different work functions in accordance with the conductivity types, so as to realize a device operation with an optimum operating threshold voltage.
This is because the operating threshold voltage of each MIS transistor is modulated as the work function (Φeff: effective work function) of the gate electrode varies at the interface between the gate electrode and the gate insulating film. To prepare gate electrodes having optimum work functions for the respective conductivity types, the process for manufacturing a CMISFET needs to be complicated, and the production costs become higher. Therefore, studies have been made to develop a technique for controlling the work functions of gate electrodes with ease.
For example, when a fully-silicided electrode including a nickel (Ni) silicide is produced, the composition is varied by adjusting the film thickness of the Ni film, so as to control the work function (see A. Lauwers et al., IEDM 2005 technical digest, p.p. 661-664 and A. Veloso, et al., VLSI-sympo. 2006 technical digest, p.p. 116-117, for example).
However, to form Ni films of different film thicknesses for the conductivity types and control the Ni—Si composition, a procedure for protecting one of the electrodes with a hard mask such as a silicon nitride film needs to be carried out twice, which complicates the manufacturing process. In A. Lauwers et al., IEDM 2005 technical digest, p.p. 661-664, the Ni—Si composition is controlled in accordance with the conductivity type by simply reducing the height of the polycrystalline Si gate electrode of the pMIS by reactive ion etching.
In A. Veloso, et al., VLSI-sympo. 2006 technical digest, p.p. 116-117, a polycrystalline SiGe layer is formed on a polycrystalline Si layer, and the selectivity in solution etching with Si is utilized to control the gate height of the polycrystalline Si layer. In this manner, the Ni—Si composition is controlled, and the work function of each electrode is adjusted in accordance with the conductivity type.
By the technique for reducing the height of each polycrystalline Si layer, however, in a case where the height is reduced to a half of the original height or less, film thickness control needs to be performed within 5 nm, and the production variation in the plane of the Si substrate becomes larger. As a result, the yield of the devices as LSI circuits becomes lower. In a case where a Ni silicide having a larger Ni/Si composition ratio than 1 is formed in a p-channel MIS transistor by the above technique, the volume of the electrode increases during the formation of the Ni silicide, and mechanical stress is applied to the gate insulating film located immediately below the gate electrode. As a result, defects are formed in the gate insulating film, and the insulating properties are degraded. The mechanical stress is also applied to the channel region, and its size varies with the production variation. This increases the variation in mobility, and degrades the circuit performance.